In contrast to conventional planar metal-oxide-semiconductor field-effect transistors (“MOSFETs”), multi-gate transistors incorporate two or more gates into a single device. Relative to single gate transistors, multi-gate transistors reduce off-state current leakage, increase on-state current flow, and reduce overall power consumption. Multi-gate devices having non-planar topographies also tend to be more compact than conventional planar transistors and consequently permit higher device densities to be achieved.
One known type of non-planar, multi-gate transistor, commonly referred to as a “FinFET,” includes two or more parallel fins (“fin structures”) formed on a substrate, such as a silicon-on-insulator substrate. The fin structures extend along a first axis between common source and drain electrodes. At least one conductive gate structure is formed over the fin structures and extends along a second axis generally perpendicular to the first axis. More specifically, the gate extends across and over the fin structures such that an intermediate region of the gate conformally overlays three surfaces of each fin (i.e., an upper surface, a first sidewall surface, and a second opposing sidewall surface of each fin). The surfaces form the channel of the gate.
While providing the advantages noted above, FinFETs and other non-planar multi-gate devices (e.g., triFETs) can be somewhat difficult to fabricate due to their unique topographies, particularly at advanced technology nodes. For example, it is difficult to form fin structures having substantially uniform thicknesses and heights and which are separated by uniform recess widths. Conventional fin fabrication processes typically form recesses in a semiconductor material to define adjacent fin structures. Because conventional processes form recesses with varying depths and widths, the fin structures are formed with non-uniform thicknesses and heights.
Accordingly, it is desirable to provide methods for fabricating integrated circuits with improved semiconductor fin structures. Also, it is desirable to provide methods for fabricating integrated circuits with semiconductor fin structures wherein the methods incorporate use of uniform mask segments having planar upper surfaces and that are separated by uniform distances. It is also desirable to provide methods for fabricating semiconductor fin structures for integrated circuits. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.